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1 isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design ) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2009, 2010. all rights reserved all other trademarks mentioned are the property of their respective owners. radiation hardened, high performance industry standard single-ended current mode pwm controller isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh the isl7884xasrh is a high performance, radiation hardened drop-in replacement for the popular 28c4x and 18c4x pwm controllers suitable for a wide range of power conversion applications including boost, flyback, and isolated output configurations. its fast signal propagation and output switching characteristics make this an ideal product for existing and new designs. features include up to 13.2v operation, low operating current, 90a typ start-up current, adjustable operating frequency to 1mhz, and high peak current drive capability with 50ns rise and fall times. specifications for rad hard qml devices are controlled by the defe nse supply center in columbus (dscc). the smd numbers listed in the ordering information must be used when ordering. detailed electrical specifications for the isl788xasrh are contained in smd 5962-07249. a ?hot-link? is provided on our website for downloading. features ? electrically screened to dscc smd # 5962-07249 ? qml qualified per mil-prf-38535 requirements ?1a mosfet gate driver ? 90a typ start-up current, 125a max ? 35ns propagation delay current sense to output ? fast transient response with peak current mode control ? 9v to 13.2v operation ? adjustable switching frequency to 1mhz ? 50ns rise and fall times with 1nf output load ? trimmed timing capacitor discharge current for accurate deadtime/maximum duty cycle control ? 1.5mhz bandwidth error amplifier ? tight tolerance voltage reference over line, load and temperature ? 3% current limit threshold ? pb-free available (rohs compliant) applications ? current mode switching power supplies ? isolated buck and flyback regulators ? boost regulators ? direction and speed control in motors ? control of high current fet drivers part number rising uvlo max. duty cycle isl78840asrh 7.0 100% isl78841asrh 7.0 50% isl78843asrh 8.4v 100% isl78845asrh 8.4v 50% pin configurations isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh (8 ld flatpack) top view isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh (8 ld sbdip) top view 8 7 6 5 2 3 4 1 comp fb cs rtct v ref v dd out gnd comp fb cs rtct 1 2 3 4 8 7 6 5 v ref v dd out gnd august 19, 2010 fn6991.1
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 2 fn6991.1 august 19, 2010 ordering information ordering number part number temp. range (c) package (pb-free) pkg. dwg. # isl78840asrhvx/sample isl78840asrhvx/sample -55 to +125 die isl78840asrhf/proto isl78840asrhf/proto (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724901qxc isl78840asrhqf (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724901vxc isl78840asrhvf (notes 1, 2) -55 to +125 8 ld flatpack k8.a isl78840asrhd/proto isl78840asrhd/proto (n otes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724901qpc isl78840asrhqd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724901vpc isl78840asrhvd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 isl78841asrhvx/sample isl78841asrhvx/sample -55 to +125 die isl78841asrhf/proto isl78841asrhf/proto (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724902qxc isl78841asrhqf (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724902vxc ISL78841ASRHVF (notes 1, 2) -55 to +125 8 ld flatpack k8.a isl78841asrhd/proto isl78841asrhd/proto (n otes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724902qpc isl78841asrhqd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724902vpc isl78841asrhvd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 isl78843asrhvx/sample isl78843asrhvx/sample -55 to +125 die isl78843asrhf/proto isl78843asrhf/proto (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724903qxc isl78843asrhqf (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724903vxc isl78843asrhvf (notes 1, 2) -55 to +125 8 ld flatpack k8.a isl78843asrhd/proto isl78843asrhd/proto (n otes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724903qpc isl78843asrhqd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724903vpc isl78843asrhvd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 isl78845asrhvx/sample isl78845asrhvx/sample -55 to +125 die isl78845asrhf/proto isl78845asrhf/proto (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724904qxc isl78845asrhqf (notes 1, 2) -55 to +125 8 ld flatpack k8.a 5962r0724904vxc isl78845asrhvf (notes 1, 2) -55 to +125 8 ld flatpack k8.a isl78845asrhd/proto isl78845asrhd/proto (n otes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724904qpc isl78845asrhqd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 5962r0724904vpc isl78845asrhvd (notes 1, 2) -55 to +125 8 ld sbdip d8.3 notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. for moisture sensitivity level (msl), please see device in formation page for isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh . for more information on msl please see techbrief tb363 . isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 3 fn6991.1 august 19, 2010 functional block diagram t q q on 150k 100k v dd cs out fb rtct gnd v ref pwm comparator reset dominant 2.5v enable 8.4ma 2.9v 1.0v oscillator comparator <10ns + - start/stop uv comparator v ref 5v + - + - 100mv error amplifier + - v ref + - on + - s r q q comp v ref uv comparator 4.65v 4.80v + - a = 0.5 + - clock 1.1v clamp 2r r vf total = 1.15v a v ref fault ok v dd 36k isl78841a, only isl78845a isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 4 fn6991.1 august 19, 2010 typical application - 48v in put dual output flyback v in + v in - return t1 q3 36v to 75v vr1 +1.8v +3.3v c1 c2 c3 r1 r3 c4 q1 r4 cr6 c5 r22 u2 cr2 cr5 cr4 c17 r21 u3 r16 c14 c13 r15 r19 r17 r18 r20 c15 c16 c12 c11 r13 c8 r10 r6 cr1 + + c21 c19 c22 c20 + + c6 isl7884xasrh v dd rtct cs fb out comp v ref gnd r26 r27 u4 r28 isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 5 fn6991.1 august 19, 2010 typical application - boost converter vin+ vin- c1 q1 r1 r4 cr1 c9 r7 c2 c5 c6 c7 r3 + r2 c4 l1 c3 vin+ u1 isl7884xasrh out cs rtct fb comp v ref v dd gnd +vout r6 r5 return c10 c8 r8 r9 isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 6 fn6991.1 august 19, 2010 electrical specifications recommended operating conditions unless ot herwise noted. refer to block diagram and typical application schemati c on page 3 and page 4. v dd = 13.2v, r t = 10k , c t = 3.3nf, t a = -55 to +125c . typical values are at t a = +25c. parameter test conditions min typ max units undervoltage lockout start threshold isl78840a, isl78841a - 7.0 - v isl78843a, isl78845a - 8.4 - v stop threshold isl78840a, isl78841a - 6.6 - v isl78843a, isl78845a - 7.6 - v hysteresis isl78840a, isl78841a - 0.4 - v isl78843a, isl78845a - 0.8 - v start-up current, i dd v dd < start threshold - 90 - a v dd < start threshold, 100krad - 300 - a operating current, i dd (note 3) - 2.9 - ma operating supply current, i d includes 1nf gate loading - 4.75 - ma reference voltage overall accuracy over line (v dd = 9v to 13.2v), load 1ma and 10ma, temperature -5.000- v long term stability t a = +125c, 1000 hours (note 4) - 5 - mv current limit, sourcing - - - ma current limit, sinking - - - ma current sense input bias current v cs = 1v - - - a input signal, maximum - 1.00 - v gain, a cs = v comp / v cs 0 < v cs < 910mv, v fb = 0v - 3.0 - v/v cs to out delay -35-ns error amplifier open loop voltage gain (note 4) - 90 - db unity gain bandwidth (note 4) - 1.5 - mhz reference voltage v fb = v comp -2.500- v fb input bias current v fb = 0v - -0.2 - a comp sink current v comp = 1.5v, v fb = 2.7v - - - ma comp source current v comp = 1.5v, v fb = 2.3v - - - ma comp voh v fb = 2.3v - - - v comp vol v fb = 2.7v - - - v psrr frequency = 120hz, v dd = 9v to 13.2v (note 4) -80-db oscillator frequency accuracy initial, t a = +25c - 51 - khz frequency variation with v dd t a = +25c, (f 13.2v - f 9v )/f 12v -0.2- % temperature stability (note 4) - 5 -% amplitude, peak-to-pe ak static test - 1.75 - v rtct discharge voltage (valley voltage) static test - 1.0 - v discharge current rtct = 2.0v - 7.8 - ma output isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 7 fn6991.1 august 19, 2010 gate voh v dd to out, i out = -100ma - 1.0 - v gate vol out to gnd, i out = 100ma - 1.0 - v peak output current c out = 1nf (note 4) - 1.0 - a rise time c out = 1nf - 35 - ns fall time c out = 1nf - 20 - ns output off state leakage v dd = 5v - - - a pwm maximum duty cycle (isl78840a, isl78843a) comp = v ref - 96.0 - % maximum duty cycle (isl78841a, isl78845a) comp = v ref - 48.0 - % minimum duty cycle comp = gnd - - - % notes: 3. this is the v dd current consumed when the device is active but not switching. does not include gate drive current. 4. limits established by characterizat ion and are not production tested. 5. see tests performed with vref by pass capacitor of 0.22f and f sw = 200khz. seb/l tests done on a standalone open loop configuration. set tests done in a closed loop configuratio n. for sel no hard latch requ iring manual intervention were observed. for more information see see test report xxxx. electrical specifications recommended operating conditions unless ot herwise noted. refer to block diagram and typical application schemati c on page 3 and page 4. v dd = 13.2v, r t = 10k , c t = 3.3nf, t a = -55 to +125c . typical values are at t a = +25c. parameter test conditions min typ max units isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 8 fn6991.1 august 19, 2010 pin descriptions rtct - this is the oscillator timing control pin. the operational frequency and maximum duty cycle are set by connecting a resistor, rt, between v ref and this pin and a timing capacitor, ct, from this pin to gnd. the oscillator produces a sawtooth waveform with a programmable frequency range up to 2.0mhz. the charge time, t c , the discharge time, t d , the switching frequency, f, and the maximum duty cycle, d max , can be approximated from the equations 1 through 4: the formulae have increased error at higher frequencies due to propagation delays. figure 4 may be used as a guideline in selecting the capacitor and resistor values required for a given switching frequency for the isl78841, isl78845asrh. the value for the isl78840, isl78843asrh will be twice that shown in figure 4. comp - comp is the output of the error amplifier and the input of the pwm comparator. the control loop frequency compensation network is connected between the comp and fb pins. fb - the output voltage feedback is connected to the inverting input of the error am plifier through this pin. the non-inverting input of the error amplifier is internally tied to a reference voltage. cs - this is the current sense input to the pwm comparator. the range of the input signal is nominally 0v to 1.0v and has an internal offset of 100mv. gnd - gnd is the power and small signal reference ground for all functions. out - this is the drive output to the power switching device. it is a high current output capable of driving the gate of a power mosfet with peak currents of 1.0a . this gate output is actively held low when v dd is below the uvlo threshold. v dd - v dd is the power connection for the device. the total supply current will depend on the load applied to out. total i dd current is the sum of the operating current and the average output current. knowing the operating frequency, f, and the mosfet gate charge, qg, typical performance curves figure 1. frequency vs temperature figure 2. reference voltage vs temperature figure 3. ea reference vs temperature figure 4. resistance for ct capacitor values given -60 -40 -20 0 20 40 60 80 100 120 140 0.98 0.99 1.00 1.01 temperature (c) normalized frequency -60 -40 -20 0 20 40 60 80 100 0.995 0.996 0.997 0.998 0.999 1.000 1.001 temperature (c) normalized v ref 140 120 -60 -40 -20 0 20 40 60 80 100 120 140 0.996 0.997 0.998 1.000 1.001 temperature (c) normalized ea reference 110100 1 10 100 10 3 rt (k ) frequency (khz) 100pf 220pf 330pf 470pf 1.0nf 2.2nf 3.3nf 4.7nf 6.8nf t c 0.533 rt ct ?? (eq. 1) t d rt ? ct in 0.008 rt 3.83 ? ? 0.008 rt 1.71 ? ? --------------------------------------------- ? ? ? ? ?? (eq. 2) f 1t c t d + () ? = (eq. 3) dt c f ? = (eq. 4) isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 9 fn6991.1 august 19, 2010 the average output current can be calculated from equation 5: to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the v dd and gnd pins as possible. v ref - the 5.00v reference voltage output. +1.0/-1.5% tolerance over line, load and operating temperature. the recommended bypass to gnd cap is in the range 0.1f to 0.22f. a typical value of 0.15f can be used. functional description features the isl7884xasrh current mode pwm makes an ideal choice for low-cost flyback and forward topology applications. with its greatly improved performance over industry standard parts, it is the obvious choice for new designs or existing designs which require updating. oscillator the isl7884xasrh has a sawtooth oscillator with a programmable frequency range to 2mhz, which can be programmed with a resistor from v ref and a capacitor to gnd on the rtct pin. (please refer to figure 4 for the resistor and capacitance required for a given frequency). soft-start operation soft-start must be implemented externally. one method, illustrated below, clamps the voltage on comp. the comp pin is clamped to the voltage on capacitor c 1 plus a base-emitter junction by transistor q 1 . c 1 is charged from v ref through resistor r 1 and the base current of q 1 . at power-up c 1 is fully discharged, comp is at ~0.7v, and the duty cycle is zero. as c1 charges, the voltage on comp increases, and the duty cycle increases in proportion to the voltage on c 1 . when comp reaches the steady state operating point, the control loop takes over and soft start is complete. c 1 continues to charge up to v ref and no longer affects comp. during power down, diode d1 quickly discharges c1 so that the soft start circuit is properly initialized prior to the next power on sequence. gate drive the isl7884xasrh is capable of sourcing and sinking 1a peak current. to limit the peak current through the ic, an optional external resistor may be placed between the totem-pole output of the ic (out pin) and the gate of the mosfet. this small series resistor also damps any oscillations caused by the resonant tank of the parasitic inductances in the traces of the board and the fet?s input capacitance. tid environment of >50krads requires the use of a bleeder resistor of 10k from out pin to gnd. slope compensation for applications where the maximum duty cycle is less than 50%, slope compensation may be used to improve noise immunity, particularly at lighter loads. the amount of slope compensation requir ed for noise immunity is determined empirically, but is generally about 10% of the full scale current feedback si gnal. for applications where the duty cycle is greater than 50%, slope compensation is required to prevent instability. slope compensation may be accomplished by summing an external ramp with the cu rrent feedback signal or by subtracting the external ramp from the voltage feedback error signal. adding the external ramp to the current feedback signal is the more popular method. from the small signal current-mode model [1] it can be shown that the naturally-sampled modulator gain, fm, without slope compensation is calculated in equation 6: where sn is the slope of the sawtooth signal and tsw is the duration of the half-cycle. when an external ramp is added, the modulator gain becomes equation 7: where se is slope of the external ramp and becomes equation 8: the criteria for determining the correct amount of external ramp can be determined by appropriately setting the damping factor of the double-pole located at the switching frequency. the do uble-pole will be critically damped if the q-factor is set to 1, over-damped for q < 1, and under-damped for q > 1. an under-damped condition may result in current loop instability. i out qg f = (eq. 5) figure 5. soft-start v ref comp gnd isl7884xasrh c1 q1 d1 r1 fm 1 sntsw ------------------- - = (eq. 6) fm 1 sn se + () tsw ------------------------------------ - 1 m c sntsw -------------------------- == (eq. 7) m c 1 se sn ------- + = (eq. 8) q 1 m c 1d ? () 0.5 ? () ------------------------------------------------- = (eq. 9) isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 10 fn6991.1 august 19, 2010 where d is the percent of on time during a switching cycle. setting q = 1 and solving for se yields equation 10: since sn and se are the on time slopes of the current ramp and the external ramp, respectively, they can be multiplied by t on to obtain the voltage change that occurs during t on . where v n is the change in the current feedback signal ( i) during the on time and ve is the voltage that must be added by the external ramp. for a flyback converter, vn can be solved for in terms of input voltage, current transducer components, and primary inductance, yielding equation 12: where r cs is the current sense resistor, f sw is the switching frequency, l p is the primary inductance, v in is the minimum input voltage, and d is the maximum duty cycle. the current sense signal at the end of the on time for ccm operation is equation 13: where v cs is the voltage across the current sense resistor, l s is the secondary winding inductance, and i o is the output current at current limit. equation 13 assumes the voltage drop across the output rectifier is negligible. since the peak current limit threshold is 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value when the output load is at the current limit threshold as shown in equation 14. substituting equations 12 an d 13 into equation 14 and solving for r cs yields equation 15: adding slope compensation is accomplished in the isl7884xasrh using an external buffer transistor and the rtct signal. a typical application sums the buffered rtct signal with the current sense feedback and applies the result to the cs pin as shown in figure 6. assuming the designer has selected values for the rc filter (r 6 and c 4 ) placed on the cs pin, the value of r 9 required to add the appropriate external ramp can be found by superposition. the factor of 2.05 in equation 16 arises from the peak amplitude of the sawtooth waveform on rtct minus a base-emitter junction drop. that voltage multiplied by the maximum duty cycle is the voltage source for the slope compensation. rearranging to solve for r 9 yields equation 17: the value of r cs determined in equation 15 must be rescaled so that the current sense signal presented at the cs pin is that predicted by equation 13. the divider created by r 6 and r 9 makes this necessary. example: v in = 12v v o = 48v l s = 800h ns/np = 10 lp = 8.0h i o = 200ma switching frequency, f sw = 200khz duty cycle, d = 28.6% r 6 = 499 solve for the current sense resistor, r cs , using equation 15. s e s n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 10) v e v n 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = (eq. 11) v e dt ? sw v in r cs ?? l p ---------------------------------------------------- 1 -- - 0.5 + ?? ?? 1 1d ? ------------- 1 ? ?? ?? = v (eq. 12) v cs n s r cs ? n p ------------------------ i o 1d ? () v o f ?? sw 2l s -------------------------------------------- + ?? ?? ?? = v (eq. 13) v e v cs + 1 = (eq. 14) r cs 1 df sw v in ?? l p ------------------------------- 1 -- - 0.5 + 1d ? ----------------- - 1 ? ?? ?? ?? ?? ? n s n p ------ - i o 1d ? () v o f sw ?? 2l s -------------------------------------------- + ?? ?? ?? ? + ------------------------------------------------------------------------------------------------------------------------------- --------------------- - = (eq. 15) cs rtct r6 c4 r9 isl78843asrh v ref figure 6. slope compensation v e 2.05d r 6 ? r 6 r 9 + --------------------------- - = v (eq. 16) r 9 2.05d v e ? () r 6 ? v e --------------------------------------------- - = (eq. 17) r cs r 6 r 9 + r 9 -------------------- - r cs ? = (eq. 18) isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 11 fn6991.1 august 19, 2010 r cs = 295m determine the amount of voltage, ve, that must be added to the current feedback signal using equation 12. ve = 92.4mv using equation 17, solve for the summing resistor, r 9 , from ct to cs. r 9 = 2.67k determine the new value of r cs (r? cs ) using equation 18. r? cs = 350m additional slope compensation may be considered for design margin. the above discussion determines the minimum external ramp that is required. the buffer transistor used to create the external ramp from rtct should have a sufficiently high gain (>200) so as to minimize the required base current. whatever base current is required reduces the charging current into rtct and will reduce the oscillator frequency. fault conditions a fault condition occurs if v ref falls below 4.65v. when a fault is detected out is disabled. when v ref exceeds 4.80v, the fault condition clears, and out is enabled. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plane must be employed. a unique section of the ground plane must be designated for high di/dt currents associated with the output stage. v dd should be bypassed directly to gnd with good high frequency capacitors. references [1] ridley, r., ?a new continuous-time model for current mode control?, ieee transactions on power electronics, vol. 6, no. 2, april 1991. isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 12 fn6991.1 august 19, 2010 die map isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 13 fn6991.1 august 19, 2010 products intersil corporation is a leader in the design and manuf acture of high-performance analog semiconductors. the company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentat ion and related parts, please see the respective device information page on intersil.com: isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informat ional purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 4/22/10 fn6991.1 added electrical spec table showing only the typical values. removed boldface over-temp limit notes. 4/8/10 added sbdip part s, pinout and flatpack & sbdip pods. 12/21/09 fn6991.0 initial pre-release isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 14 fn6991.1 august 19, 2010 isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh package outline drawing k8.a 8 lead ceramic metal seal flatpack package rev 1, 1/10 lead finish side view top view -d- -c- 0.265 (6.75) 0.115 (2.92) 0.026 (0.66) min 0.265 (6.73) seating and 0.180 (4.57) 0.03 (0.76) min base plane -h- 0.09 (0.23) 0.005 (0.13) pin no. 1 id area 0.050 (1.27 bsc) 0.022 (0.56) 0.015 (0.38) min 0.245 (6.22) 0.070 (1.18) 0.170 (4.32) 0.370 (9.40) 0.250 (6.35) 0.04 (0.10) 0.245 (6.22) 1. adjacent to pin one and shall be loca ted within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. alternately, a tab may be used to identify pin one. 2. of the tab dimension do not apply. 3. the maximum limits of lead dimensions (section a-a) shall be measured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 4. 5. shall be molded to the bottom of the package to cover the leads. 6. meniscus) of the lead from the body. dimension minimum shall be reduced by 0.0015 inch (0. 038mm) maximum when solder dip lead finish is applied. 7. 8. notes: 0.015 (0.38) 0.008 (0.20) pin no. 1 id optional 1 2 4 6 3 dimensioning and tolerancing per ansi y14.5m - 1982. controlling dimension: inch. index area: a notch or a pin one identification mark shall be located if a pin one identification mark is used in addition to a tab, the limits measure dimension at all four corners. for bottom-brazed lead packages, no organic or polymeric materials dimension shall be measured at the point of exit (beyond the section a-a base metal 0.007 (0.18) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) max 0.022 (0.56) 0.015 (0.38)
isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh 15 intersil products are manufactured, assembled and tested utilizing iso9000 qu ality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, th e reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accura te and reliable. however, no re sponsibility is assumed by inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which ma y result from its use. no licen se is granted by implication o r otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn6991.1 august 19, 2010 for additional products, see www.intersil.com/product_tree isl78840asrh, isl78841asrh, isl78843asrh, isl78845asrh ceramic dual-in-line me tal seal packages (sbdip) notes: 1. index area: a notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identification shall not be used as a pin one identification mark. 2. the maximum limits of lead di mensions b and c or m shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 4. corner leads (1, n, n/2, and n/2+1) may be configured with a partial lead paddle. for this co nfiguration dimension b3 replaces dimension b2. 5. dimension q shall be measured from the seating plane to the base plane. 6. measure dimension s1 at all four corners. 7. measure dimension s2 from the top of the ceramic body to the nearest metallization or lead. 8. n is the maximum number of terminal positions. 9. braze fillets shall be concave. 10. dimensioning and tolerancing per ansi y14.5m - 1982. 11. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d8.3 mil-std-1835 cdip2-t8 (d-4, configuration c) 8 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.405 - 10.29 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n8 88 rev. 0 4/94

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